Intel has detailed Xeon 6+ “Clearwater Forest,” a server CPU built for density and efficiency. It combines the new Darkmont E-core architecture with the 18A process, Foveros Direct 3D die stacking, and a disaggregated design.
Intel is guiding 1.9× higher performance versus its first-gen E-core Xeon at similar power, plus ~23% better efficiency across typical load.
What’s inside Clearwater Forest
A tile-based package with three compute base tiles, twelve 18A core tiles, and two I/O tiles connected with EMIB and Foveros Direct. Built to cram in cores without melting the rack.
- Up to 288 Darkmont E-cores per socket; 576 in a 2P server
- Three Intel 3 base compute tiles with 192 MB LLC each (total 576 MB per socket)
- Twelve 18A core chiplets mounted on top via Foveros Direct 3D
- Two Intel 7 I/O tiles reused from Xeon 6 platforms
- EMIB for die-to-die and Foveros Direct with ~9 µm pitch, ~0.05 pJ/bit energy for vertical links
- PCIe 5.0 lanes and CXL 2.0 support carried over from the I/O tiles
Intel keeps splitting the SoC into the “right node for the job.” The I/O tiles stay on mature Intel 7, the coherent fabrics and LLC live on Intel 3 base tiles, and the Darkmont cores sit on 18A chiplets bonded directly above. That 3D stack is key: Foveros Direct’s copper-to-copper contacts let Intel move data between layers at femtojoules per bit, keeping latency and energy low while pushing bandwidth high. This is how you double core count versus Sierra Forest while staying in the same socket and platform family.
Darkmont E-cores: wider, hungrier, smarter
Darkmont is a wider micro-architecture with better branch prediction, bigger windows and more ports. Intel claims ~17% IPC gain over Crestmont and 2× the L2 bandwidth per 4-core module.
- ~17% IPC uplift vs Sierra Forest’s Crestmont (SPECint-rate guidance)
- 4-core modules share a 4 MB L2 with 2× bandwidth
- Nine-wide front end feeding an eight-wide backend; 26 execution ports
- Reliability: ECC at L1, improved error handling, optional lockstep pairs for safety-critical use
Darkmont grows the front end and deepens the out-of-order engine to keep server-class code saturated. More fetch/decode width, beefed-up branch prediction and extra integer/vector throughput mean better per-core work at the same power. The L2 remains shared per 4-core module but doubles bandwidth, which matters when 288 cores are all tugging on memory.
18A process: RibbonFET plus backside power
18A combines Intel’s gate-all-around RibbonFET transistors with PowerVia backside power delivery. The goal is higher performance per watt and more routing area for signals.
- RibbonFET for tighter channel control and better Vmin behaviour
- PowerVia moves power rails under the transistors, freeing signal tracks and reducing IR drop
- Intel is tracking 18A for high-volume products from late 2025 into 2026, with server and client parts both using it (Clearwater Forest, Panther Lake).
Moving power delivery under the device layer cleans up the top-side metal for signalling and can lift standard-cell utilisation. That’s one enabler for stacking smaller 18A core tiles above larger Intel 3 base compute dies without strangling routing.
Memory, I/O and accelerators
The reused Xeon 6 I/O tiles keep the platform stable but add enough bandwidth to feed the core swarm. Think DDR5-8000, PCIe 5.0 and CXL 2.0 across two I/O tiles.
- 12 channels of DDR5 per socket at up to 8 GT/s
- PCIe 5.0 lanes with 32 lanes per tile supporting CXL 2.0, duplicated across two I/O tiles
- UPI links and on-package accelerators carry over from the existing Xeon 6 platform
- Target TDP envelope: roughly 300–500 W per socket, depending on SKU
Reusing the I/O tiles matters for operators: socket compatibility and platform reuse shorten validation cycles. CXL 2.0 means memory pooling options for dense microservices and inference. With 12 DDR5 channels, memory bandwidth scales to keep those E-cores busy instead of thrashing the mesh.
Real-world impact: density, power, cost
Intel pitches 1.9× more performance at similar power vs first-gen E-core Xeon, ~23% efficiency gains across the utilisation curve, and up to 8:1 server consolidation against older racks. UAE data centres chasing lower power and floor space should pay attention.
- 1.9× performance uplift claim vs Sierra Forest class at like-for-like power
- ~23% better efficiency across typical load levels
- Up to 8:1 consolidation replacing 5-year-old racks
- Dual-socket can hit 576 cores and over 1.1 GB of shared LLC per system
Core-scale CPUs won’t replace GPUs for training any time soon, but for web services, GRPC microservices, caches and a lot of inference, density and perf-per-watt wins capex and opex arguments. If you operate in the UAE with tight cooling envelopes and expensive space, cutting racks while boosting capacity is a very easy sell.
When will Xeon 6+ Clearwater Forest be available?
Intel is lining up 18A products into late 2025 and 2026. Xeon 6+ is expected to land in the first half of 2026. UAE availability follows global launch windows.
How is this different from Sierra Forest?
Twice the core count per socket, a new Darkmont E-core with ~17% higher IPC, 5× more shared LLC, and higher memory speed with 12 DDR5 channels. It also uses 18A and Foveros Direct for 3D stacking.
Is Clearwater Forest good for AI?
For inference and CPU-bound orchestration, yes. It’s about density and perf-per-watt. Training still prefers accelerators. CXL 2.0 and big memory help with serving.
What about PCIe and CXL?
The platform keeps PCIe Gen 5 and CXL 2.0 from Xeon 6 I/O tiles, with lanes duplicated across two tiles per socket. Good enough for modern NICs, accelerators and pooled memory.
Why should UAE operators care?
Energy efficiency and space are expensive. Intel’s own numbers point to tangible consolidation and power savings that cut opex while keeping throughput high, which is relevant for local clouds and telcos.
