Intel’s new Data Center lead, Kevork Kechichian, sketched a simple plan: listen to customers, ship on time, and make x86 competitive again. That means two Xeon 6 tracks now — high-performance P-cores and high-density E-cores — and a next step called Clearwater Forest, branded Xeon 6+, built on Intel’s 18A process. The aim is higher core density, almost 2x memory bandwidth and better performance per watt, with platform thinking from transistor to software.
Who’s steering Intel’s data centre push
Kechichian arrives with a long hardware background across GPUs, Qualcomm, NXP and Arm. He says the job is to use Intel’s assets plus foundry to deliver what customers actually want.
- 35-year semiconductor career across design, mobile, automotive and data centres
- Belief in focusing on strengths, not fixing every weakness
- Emphasis on platform-level thinking, not just SoC hero slides
After years watching from outside, he says the draw now is leadership he trusts, engineering-first values, and the chance to use Intel Foundry as a force multiplier. Translation: align roadmaps, cut lateness, and stop leaving performance on the table due to platform bottlenecks like memory subsystems.
The three rules: customer, product, on-time
Intel’s new mantra is painfully obvious but overdue: ship what the customer asked for, make it competitive at launch, and don’t be late.
- Listen first: features, timelines, deployment realities
- Be best-in-segment at release, especially for x86
- Execute on time with quality and security baked in
Hyperscalers and telcos told Intel they want a viable x86 option again. Goodwill exists, patience doesn’t. Intel’s pitch is that relationships plus a cleaned-up execution engine can actually win sockets back.
Platform, not parts: where Intel says it wins next
The focus shifts from cores alone to whole-platform outcomes: reliability, security, power delivery, memory choices and I/O pipes.
- Model the full stack pre-silicon, not just micro-benchmarks
- Treat memory types and topology as first-order performance levers
- Invest in PCIe, CXL and die-to-die fabrics as data plumbing
- Keep open-source strong, but use it to create Intel advantage
Data centres fail in the mess between components: racks, nodes, firmware, drivers, orchestration. Intel wants deployments that don’t melt, stall or finger-point. Expect more work on telemetry, power integrity, NUMA behaviour and software bring-up so operators can stand up racks faster and troubleshoot with familiar tools.
Telco focus: Ericsson and dual-mode 5G
One marquee collaboration is with Ericsson on dual-mode 5G, where core count per socket and perf-per-watt decide total cost and site footprint.
- Dense E-cores target baseband and edge compute
- Power-performance multipliers vs older Xeon generations
- Aim: smaller physical footprint, predictable latency, easier fleet management
For operators, more capacity in the same RU count and lower energy per bit is real money. Intel’s message is that Sierra Forest-class nodes let NEPs pack more sectors and services per rack without blowing the budget on power and cooling.
Clearwater Forest: Xeon 6+ on 18A
The next platform step, “Clearwater Forest,” brands as Xeon 6+ and moves to Intel’s 18A process with architectural and I/O bumps.
- ~2x core density vs current E-core generation
- Nearly 2x memory bandwidth
- Better performance per watt as a design goal
- Part of a platform story from transistor to high-level software
It’s the logical continuation of the density track. More cores per socket plus fatter memory pipes should lift throughput workloads and micro-service fleets. The key test won’t be a slide; it will be shipping windows, OEM availability, and real-world perf-per-watt in mixed clusters.
