AMD detailed its full Zen 6 architecture for EPYC Venice server chips. Wccftech’s full breakdown gives AMD’s claim as a 27% average IPC gain over Zen 5, with up to 256 cores per socket.
That 27% is a server number. AMD measured only enterprise, cloud, and AI workloads, and it didn’t test a single client application, so it says nothing about games or desktop Ryzen yet. AMD also got it by comparing a fixed-frequency Zen 5 chip against a 16-core Zen 6c configuration: a like-for-like core comparison, not a full-chip one. No independent tests of Zen 6 IPC exist yet.
The Register reads AMD’s data as a range of 20% to 31% for cloud and AI work, with boost clocks from 4.1 to 5.3 GHz. By its own arithmetic, a 4.1 GHz Zen 6c Venice chip should match a Zen 5 Turin chip running at 5 GHz.
The bigger design choice is the split into two cores with the same instruction set. Zen 6c is the dense one, packing 32 cores and 128 MB of L3 cache into a single chiplet, double Zen 5c’s maximum. Eight of those chiplets make the 256-core parts. Standard Zen 6 holds 12 cores per chiplet, up from eight, and tops out at 96 cores. It clocks higher, though: the EPYC 9686F reaches 5.3 GHz, the fastest EPYC yet.
| Feature | Zen 5c | Zen 6c |
|---|---|---|
| Return address stack | 52 entries | 64 entries |
| Op cache | 6K entries | 6.75K entries |
| Micro-ops per cycle from op cache | 12 | Up to 18 |
| Physical register file | 240 entries | 352 entries |
| Cores per dense chiplet | 16 | 32 |
Elsewhere in the core, AMD added an 80-entry load queue, a 128-entry store queue and native AVX-512 FP16 support. The chips are built on TSMC’s 2 nm-class N2 node. Memory also gets a big lift: 16 DDR5 channels run at up to 12.8 GT/s on MRDIMMs, for a peak of 1.6 TB/s per socket. Standard RDIMMs top out at DDR5-8000.
AMD’s own comparisons go further. It claims a 256-core Venice chip delivers up to 2.2 times the SPECrate throughput of Nvidia’s 88-core Vera. We covered that rivalry in our earlier Venice report. It also claims up to 1.3 times the per-core performance of Intel’s Xeon 6980P.
Server chips going first fits AMD’s priorities. Lisa Su recently called the company “data center first”, with data centre revenue nearly doubling to $8.5 billion last quarter as gaming revenue fell. AMD plans its next Ryzen desktop chips on the same Zen 6 chiplet, but it hasn’t shown them. The Register warns that server gains don’t guarantee the same on the client side.
Venice SP7 platforms have started shipping, and Microsoft Azure previewed its HDv2 instances built on the chips. AMD says the SP8 series follows in the first half of 2027. Venice-X HPC chips, carrying up to 1,152 MB of L3 per socket, are due in the second half of 2027.
